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ST5451
ISDN HDLC AND GCI CONTROLLER
MONOLITHIC ISDN ORIENTED HDLC AND GCI CONTROLLER. GCI AND W/DSI COMPATIBLE. FULLY CONTROLLING GCI AND GCI-SCIT M & C/I CHANNELS MANAGEMENT. FULLY SUPPORTING LAPB AND LAPD PROTOCOL ON B OR D CHANNEL. EASILY INTERFACEABLE WITH ANY KIND OF STANDARD NON MULTIPLEXED OR MULTIPLEXED BUS MICROPROCESSOR. DMA ACCESS WITH MULTIPLEXED BUS P CAN HANDLE AND STORE AT THE SAME TIME TWO FRAMES IN TRANSMISSION (64bytes FIFO Tx) AND EIGHT FRAMES IN RECEPTION (64bytes FIFO Rx) COMPATIBLE WITH ALL THE STMicroelectronics ISDN PRODUCT FAMILY.
SO28
ORDERING NUMBER: ST5451D
PIN CONNECTION (Top view) GENERAL DESCRIPTION ST5451 HDLC and GCI controller is a CMOS circuit fully developed by STMicroelectronics and diffused in advanced 1.2 m HCMOS3 technology. The device is intended to be used mainly in ISDN applications, in Terminal (TE) and in Line Terminations (LT). ST5451 can handle HDLC packets either on 16Kbit/s D channel or 64 Kbit/s B channel; it can work with a wide range of PCM signals going from GCI (General Circuit Interface) to DSI (Digital System Interface) to any PCM-like stream. ST5451 is a complete GCI controller designed to comply with the GCI and GCI-SCIT (Special Circuit Interface for Terminal) completely handling Monitor (M) and Command/Indicate (C/I) channels. ST5451 can be easily controlled by many different kind of microprocessors or microcontrollers having either non-multiplexed or multiplexed bus structure. ST5451 can be used in connection with ST5420/1 S Interface Devices (SID-W and SID-GCI) and ST5080 Programmable ISDN Combo (PIC) in Terminals and with ST5410 U Interface Device (UID) in Line Terminations.
March 2000
T
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is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without
ST5451
BLOCK DIAGRAM
PIN DESCRIPTION
NAME CS INT MULT I/M PIN 1 25 2 4 TYPE I O I I FUNCTION Chip Select. A low level enables ST5451 for read/write operations. Interrupt request is asserted by ST5451 when it request a service. Open drain output. Multiplexed Bus. Indicates the P bus interface selected. MULT = 1: multiplexed bus and DMA available. MULT = 0: address and data bus separated. Intel/Motorola. When MULT = 1 this pin selects either Intel or Motorola 6805 bus.
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ST5451
DEMULTIPLEXED MICROPROCESSOR BUS INTERFACE (MULT = 0)
NAME A0/A5 D0/D7 R/W E PIN 3-8 17-24 27 26 TYPE I I/O I I FUNCTION Address Bus. To transfer addresses from P to ST5451. Data Bus. To transfer data between P and ST5451. Read/Write. "1" indicates a read operation; "0" a write operation. Enable. Read/write operations are synchronized with this signal; its falling edge marks the end of an operation.
MULTIPLEXED MICROPROCESSOR BUS INTERFACE (MULT = 1 I/M = 1)
NAME AD0/AD7 WR RD ALE PIN 17-24 27 26 3 TYPE I/O I I I FUNCTION Address Data Bus. To transfer addresses and data between P and ST5451. Write. This signal indicates a write operation. Read. This signal indicates a read operation. Falling edge latches the address from the external A/D Bus.
MULTIPLEXED MICROPROCESSOR BUS INTERFACE (MULT = 1; I/M = 0)
NAME AD0/AD7 R/W DS AS PIN 17-24 27 26 3 TYPE I/O I I I FUNCTION Address Data Bus. To transfer addresses and data between P and ST5451. Read/Write. "1" Indicates a write operation; "0" a write operation. Data Strobe. Read/Write operations are synchronized with this signal: its falling edge marks the end of an operation. Address Strobe. Falling edge latches the address from the external A/D Bus.
DMA (direct memory access): only when MULT = 1
NAME DMA REQ X DMA REQ R DMA ACK X DMA ACK R PIN 7 5 8 6 TYPE O O I I FUNCTION Direct Memory Access Requests: these outputs are asserted by the device to request an exchange of byte from the memory. Direct Memory Access Acknowledge: these inputs are asserted by the DMA controller to signal to the HDLC controller that a byte is being transferred in response to a previous transfer request.
GCI INTERFACE
NAME DOUT PIN 15 TYPE I/O FUNCTION Data output for B and D channels. In GCI mode it outputs B1, B2, M and C/I channels. In TE mode (GCI-SCIT) it can invert to input data for M' and C/I' channels (See Table 2). Data input for B and D channels. In GCI mode it inputs B1, B2, M and C/I channels. In TE mode (GCI-SCIT) it can invert to output data for M' and C/I' channels (See Table 2). Data Clock. It determines the data shift rate for GCI channels on the module interface. Frame synchronization. This signal is a 8 kHz signal for frame synchronization. The front edge gives the time reference of the first bit in the frame. Data Enable. In TE mode, this pin is a normally low input pulsing high to indicate the active bit times for D channel transmit at DOUT pin. It is intended to be gated with CLK to control the shifting of data from HDLC controller to S interface device.
D IN C LK FS
12 11 13
I/O I I
DEN
10
I
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ST5451
NON GCI INTERFACE
NAME DOUT D IN C LK FS DEN PIN 15 12 11 13 10 TYPE O I I I I FUNCTION Data output. Digital output for serial data. Three modes: - HDLC Protocol multiplexed link - HDLC Protocol non multiplexed link - Non HDLC protocol (transparent Mode). Data input. Digital input for serial data. Three modes (See DOUT). Data Clock. It determines the data shift rate. Two modes: Single or double bit rate. Frame synchronization. Used in mode HDCL protocol multiplexed link. Don't care in other modes. The rising edge gives the time reference of the first bit of the frame. Data Enable. When high, enable the data transfer. on DOUT
OTHERS
NAME V DD VSS R ST ST PIN 28 14 16 9 TYPE I I I I Signal ground Reset Special Test. (Reserved) must be tied to VSS FUNCTION Positive power supply = 5V +5%
2 - FUNCTIONS 2 - 1 - Basic HDLC Functions 2 - 1 - 1 - In Receive Direction: - Channel selection In GCI channel B1 or B2 or D may be selected. B1 or B2 may be selected without M and C/I channels - Flag detection A zero followed by six consecutive ones and another zero is recognized as a flag - Zero delete A zero, after five consecutive ones within an HDLC frame, is deleted - CRC checking The CRC field is checked according to the generator polynomial X16 + X12 + X5 + 1 - Check for abort Seven or more consecutive ones are interpreted as an abort flag - Check for idle Fifteen or more consecutive ones are interpreted as "idle" - Minimum lenght checking HDLC frames with less than n bytes between start and end flag are ignored: allowed values are 3 n 6.
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This value is set by a programmable register - Address Field recognition 4 SAPI and/or 3 TEI may be recognized. Several programmable registers indicate the recognized address types. 2 - 1 - 2 - In Transmit Direction: - Shift control in TE mode D channel data are signalled by DEN pin. - Flag generation A flag is generated at the beginning and at the end of every frame. - Zero insert A zero is inserted after five consecutive ones within an HDLC frame - CRC generation The CRC field of the transmitted frame is generated according to the generator polynomial X16 + X12 + X5 + 1 - Abort sequence generation An HDLC frame may be terminated with an abort sequence under microprocessor control - Interframe time fill Flags or idle (consecutive ones) may be transmitted during the interframe time. A programmable bit selects the mode.
ST5451
2 - 2 - FIFO Structure 2 - 2 - 1 - Receive FIFO Structure In receive direction, a 64 byte FIFO memory is used. It is divided in 8 blocks of 8 bytes automatically chained. In case of a frame length of 64 bytes or less, the whole frame can be stored in the FIFO. After the first 32 bytes have been received P is interrupted and may read the available data. In case of frames longer than 64 bytes, the P is interrupted to read out the FIFO by 32 byte block. In case of several short frames, up to eight may be stored inside the FIFO. After an interrupt, one frame is available for the P. The eventual other seven frames are queuedand transferred one by one. 2 - 2 - 2 - Transmit FIFO Structure In transmit direction, a 64 byte FIFO memory is TABLE 1 - ST5451 Internal Registers
Address Hexa 00 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 3E Read Receive FIFO ISTA0 ISTA1 ISTA2 STAR MODE RFBC CA CB CC CD CE CF CIR1 CIR2 MONR1 MONR2 CCR Write Transmit FIFO ISTA0 ISTA1 ISTA2 CMDR MODE TSR CA CB CC CD CE CF CIX1 CIX2 MONX1/0 MONX1/1 MONX2/0 MONX2/1 MASK0 MASK1 MASK2 CCR
used, structured in 2 blocks of 32 bytes. ST5451 is requested to transmit after 32 bytes have been written into the FIFO. If a transmission request does not include a message end, the HDLC controller will request the next data block by an interrupt. 2 - 3 - Microprocessor Interface Three types of microprocessor interfaces are available (MULT and I/M control pins set the desired interface). - Motorola non multiplexed families. - Motorola multiplexed family (6805 type) - Intel family. You can connect ST5451 to a Direct Memory Access Controller as MC68440 or MC6450 (dual or quad channels). A programmable register indicates DMA Interface enabling.
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ST5451
TABLE 2 - CHANNEL ASSIGNMENT SELECT
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ST5451
3 - REGISTER DESCRIPTION XDU For all the register pictures MSB is on the left and LSB on the right If not otherwise stated bit are considered active at 1. entered into the XFIFO. Transmit Data Underrun A transmitted frame was terminated with an abort sequence because no data were available for transmission in XFIFO and no XME command was issued. It is not possible to transmit frame when that interrupt remains unacknowledged and XRES has not been set. Extended Interrupt 2 The interrupt reason is indicated in register ISTA2 Extented Interrupt1 The interrupt reason is indicated in register ISTA1. Interrupt Status Register 1 After RESET 01H (GCI mode only)
CIC1 EOM1 XAB1 RMR1 RAB1 XMR1
FIFOS RFIFO (read), XFIFO (write). The address range of the two FIFOs are identical. All the 32 addresses give access to the "current" FIFO location. When the closing Flag of a receive frame is detected, a status byte is available in the RFIFO. This byte has the following format:
RBC RDO CRC RAB 0 0 0 0
EXI2
EXI1
ISTA1
RBC
Receive Byte Count. The length of the received frame is n time 8 bits (n=3,4,5,...) Receive Data Overflow A part of the frame has not been lost because the receive FIFO was full CRC Check The received CRC bytes were not correct Receive Abort The received frame was not aborted
0
0
RDO
CIC1
Comman/Indicate Change A change in the value of CIR1 is detected End of Message 1 (monitor channel) MON1 has received an end of message. Monitor Transmit ABORT The received byte has not been detected in two successive frames. MON1 has sent an ABORT (A bit) to the remote transmitter. Receive Monitor Register 1 ready A byte has been received in register MONR1. Receive Abort MON1 received an ABORT from the remote receiver. Transmit Monitor Register 1 ready A byte can be stored in register MONX1 Interrupt Status Register 2 After RESET 01H (GCI and TE mode only)
CIC2 EOM2 XAB2 RMR2 RAB2 XMR2
CRC RAB
EOM1
XAB1
A status byte equal to D0H indicates a correctly received frame ISTA0
RME RME
Interrupt Status Register 0 After RESET 10H
RPF RFO XPR XDU EXI2 EXI1 0
RMR1
RAB1
Receive Message End One complete frame of length less than or equal to 32 bytes, or the last part of a frame of length greater than 32 bytes is stored in the RFIFO. Receive Pool Full 32 bytes of a frame are in RFIFO. The frame is not yet completely received. Receive Frame Overflow A complete frame was lost because no storage space was available in the RFIFO. Transmit Pool Ready One data block (32 bytes max) may be
XMR1
RPF
ISTA2
RFO
0
0
CIC2
XPR
Command/Indicate Change A change in the value of CIR2 is detected.
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ST5451
EOM2 End of Message 2 (monitor channel) MON2 has received an end of message. Monitor Transmit ABORT The received byte has not been detected in two successive frames. MON2 has sent an ABORT (A bit) to the remote transmitter. Receive Monitor Register 2 ready A byte has been received in register MONR2. Receive ABORT MON2 received an ABORT from the remote receiver. Transmit Monitor Register 2 ready A byte can be stored in register MONX2. RHR MASK0, MASK1, MASK2 After Reset FF; the three mask registers MASK0, MASK1, MASK2 are associated respectively to the three interrupt registers ISTA0, ISTA1,and ISTA2. Each interrupt source in ISTA registers can be selectively masked by setting to "1" the corresponding bit in MASK1. Interrupt sources (masked or not) are indicated when ISTA is read by the microprocessor. When an interrupt source is not masked, INT goes low. XRES CMDR Command Register After Reset 00
XHF XME RMC RMD RHR XRES M2RES M1RES
XAB2
XHF XME
HDLC frame transmission can start. Transmit Message End The last part of the frame was entered in XFIFO and can be sent. Receive Message Complete Reaction to RPF or RME interrupt. The received frame (or one pool of data) has been read and the corresponding RFIFO is free. Receive Message Delete Reaction to RPF or RME interrupt. The entire frame will be ignored. The part of frame already stored is deleted. Reset HDLC receiver Reset HDLC transmitter XFIFO is cleared and the transmitted frame (if any) is aborted. Monitor 2 Reset Reset MONITOR and C/I channels (TX and RX). Monitor 1 Reset Reset MONITOR and C/I channels (TX and RX). For the four first bits (XHF, XME, RMC, RMD), the reset is done by the device; the other bits level sensitive
RMR2
RMC
RAB2
RMD
XMR2
M2RES
M1RES
* STAR Status Register After Reset 48H
RLA DCIO 0 0 0
XDOV XFW IDLE
MODE
DMA
HDLC Mode Register After Reset 00
FL1 FL0 ITF RAC CAC NHF FLA
XDOV
Transmit Data Overflow More than 32 bytes have been written into the XFIFO. XFIFO Write enable Data can be entered into the XFIFO. IDLE State 15 or more consecutive ones have been detected on the input data line. Receive Line Active Frames or interframe flags are being received D and C/I Channels are occupied
DMA FL1/0
DMA Interface activation Frame Length Minimum frame length accepted
FL1 3 4 5 6 bytes bytes bytes bytes 0 0 1 1 FL0 0 1 0 1
XFW IDLE
RLA
ITF
DCIO
InterframeTime Fill ITF= 1 : Flags are transmitted ITF= 0 : IDLE is transmitted RAC= 1 : Activate RX RAC= 0 : deactivate RX
RAC
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ST5451
CAC Channel Activation CAC = 1 : Activate RX and TX CAC = 0 : deactivate RX and TX HDLC Function Select NHF = 1 : disable HDLC function Flag FLA = 1 : transmit shared flags FLA = 0 : transmit two flags between consecutive frames. MONX1 Monitor Transmit Register 1 After reset FFH (GCI only)
M1 M2 M3 M4 M5 M6 M7 M8
NHF FLA
The value written in MONX1 is transmitted in the outgoing Monitor channel according to GCI transfer protocol. XMR1 interrupt indicates when MONX1 is again available.
RFBC
Receive Frame Byte Counter After reset 00
RDC7 RDC6 RDC5 RDC4 RDC3 RDC2 RDC1 RDC0
MONR1 Monitor Receive Register 1 After reset FFH (GCI only)
M1 M2 M3 M4 M5 M6 M7 M8
RDC 0/7 Receive Data Count Total number of bytes of received frame without CRC. RDC 0/4 Indicate the number of bytes in the current block available in RFIFO. RDC 5/7 Indicate the number of 32 bytes blocks received. If the frame exceeds 223 bytes, RDC 5/7 hold the value "111", only RDC 4/0 continue to count modulo 32. See Table 3. The contents of the register are valid after an RME interrupt. The P must read N+1 bytes to transfer the number of bytes received and the status byte into the memory.
The value read from MONR1 gives the value of the byte received in the monitor channel according to GCI transfer protocol. RMR1 interrupt indicates when a new byte is available in MONR1 register.
CIX2
Command/Indicate Transmit Register 2 After Reset FFH (GCI and TE mode only)
1 P1 P2 P3 P4 P5 P6
1
P1/P6
Code transmitted permanently in the 2nd GCI C/I channel.
CIX1
Command/Indicate Transmit Register 1 After reset FFH (GCI only)
1 1 1 C1 C2 C3 C4
CIR2
Command/Indicate Receive Register 2 After reset FFH (GCI and TE mode selected only)
1 P1 P2 P3 P4 P5 P6
1
1
C1, C2, C3, C4: Code to be transmitted permanently in the outgoing GCI C/I channel.
P1/P6
The contents of the 2nd C/I channel; they are the different requests received from TE peripheral devices to P. Six peripherals can make a simultaneous request.
CIR1
Command/Indicate Receive Register 1 After reset FFH (GCI only)
1 1 1 C1 C2 C3 C4
1
C1, C2, C3, C4: Incoming GCI C/I channel.
MONX2 Monitor Transmit Register 2 After reset FFH (GCI and TE mode only) The value written in MONX2 is transmitted in the 2nd GCI M channel to a peripheral (if PI= 1; register CF).
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ST5451
TABLE 3
N (number of bytes in the frame received without CRC) N 1 Min 2 3 30 31 32 33 62 63 64 222 223 224 256 257 Counter 765 n 000 000 000 000 000 001 001 001 001 010 110 110 111 111 111 111 4321 0 m 00001 00010 00011 11110 11111 00000 00001 11110 11111 00000 11110 11111 11111 00000 00001 n (number of 32 bytes blocks received ) n 0 0 0 0 0 1 1 1 1 2 6 6 7 7 7 7
MONR2 Monitor Receive Register 2 After reset FFH (GCI and TE mode only) The value read from MONR2 gives the value of the byte received from M channel in 2nd GCI channel. TSR Time Slot Register After reset 00
CA
CA7
Configurationn Register A After reset 00
CA6 CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA5 CA4 CA3 CA2 CA1 CA0
SAPI 0 is recognized SAPI 63 SAPI x SAPI y TEI 127 TEI z TEI t Address filter active
CA0 = 1 CA1 = 1 CA2 = 1 CA3 = 1 CA4 = 1 CA5 = 1 CA6 = 1 CA7 = 1
TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0
In GCI mode (MDS1= 1 in CF Register) a) CCS=1 in CF Reg. (64 Kbit/s) Then: TSR2 indicates B1 or B2 TSR4/7 indicate position of GCI channel b) CCS=0 in CF Reg. (16 Kbit/s) Then: TSR4/7 indicate position of GCI and its D channel In Multiplexed Mode (MDS1=0 in CF Register) a) CCS=1 in CF Reg. (64 Kbit/s) Then: TSR2/7 indicate channel position in the 64 time slots multiplex b) CCS=0 in CF Reg. (16 Kbit/s) Then: TSR0/7 indicate channel position in the 256 time slots multiplex.
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CB
Configuration register B After reset 00 Content of CB indicate SAPI x value
High Order 6 Bits SAPI 0 0
CC
Configuration Register C After reset 00 Content of CC indicate SAPI y value
High Order 6 Bits SAPI 0 0
ST5451
CD Configuration Register D After reset 00 Content of CD indicate TEI z value.
7 High Order Bits TEI 0
SC = 1 means "an 8Kbit/s or 56Kbit/s subchannel inside a 16Kbit/s or 64kbit/sis used" (see MAS/SSC) PI Peripheral Interface (only if TE=1) PI = 1: CIX2, CIR2, MONX2, MONR2, active
CE
Configuration Register E After reset 00 Content of CE indicate TEI t value.
7 High Order Bits TEI 0
VZDOUT When level 1 device is inactive (i.e. CIR1 = DI = 1111) and GCI has to be waken up (i.e. TIM = 0000 in CIX1), DOUT is set to zero requiring FS and CLK if VZ DOUT=1. MDS1 Mode Bit 1 MDS1 = 1:GCI mode MDS1 = 0: Multiplexed mode Mode Bit 0 MDS0 = 1: Multiplexer and Demultiplexer are active. MDS=0 No multiplexer. Configuration Register 00 After reset 00
AD2 AD1 AD0 CRS TRI
CF
Configuration Register F After 00
MDS0
TE MAS/SSC CCS CMS/SC PI VZDOUT MDS1 MDS0
TE
TE mode TE = 1 : the frame is constitued by three GCI channels (GCI-SCIT)
CCR
MAS/SSC If CCS = 0, TE = 1, MDS0 and MDS1 = 1 (i.e. GCI mode, TE mode, 16 Kbit/s) MAS/SSc is MAS and: MAS = 0 means "Slave device" MAS = 1 means "Master device" If SC = 1 (i.e. a sub-channel is selected) MAS/SSC is SSC; if 16Kb is selected SSC chooses between first on second bit of the stream while, if 64Kb is selected SSC chooses between first or last seven bits of the stream (see TABLE 2 and CMS/SC) CCS Channel Capacity Selection CCS = 1: 64 Kb/s CCS = 0: 16 Kb/s.
TLP ADDR AD3
TLP
Test Loop TLP = 1: The transmitter is internally connected to the receiver; the transmit output is not activated. The digital interface must be activated to provide the bit clock and frame Synchro. Address Recognized If TE = 1 and PI = 1 ADDR = 1: The first byte received in MONR2 is compared with AD0/3. If equal the message is accepted, otherwise is ignored. ADDR = 0: The message is always accepted. When PI = 1, is the component address. Address bit used to access D and C/I channels (TE = CMS =1, CCS = 0). Clock Rate Selection CRS = 1: Clock frequency is twice the data rate (GCI). CRS = 0: Clock frequency and data rate are identical. Tristate TRI = 1: DOUT in tristate TRI = 0: DOUT in open drain.
ADDR
CMS/SC If CCS = 0, TE = 1, MDS0 and MDS1 = 1 (i.e. GCI mode, TE mode, 16Kbit/s) CMS/SC is CMS (Contention mode selection) and: CMS = 1 means "D and C/I channel access procedure active" CMS = 0 means "D and C/Z channel access procedure active" If CCS = 1 and TE = 1 CMS/SC is SC (Subchannel) and: SC = 0 means "16Kbit/s or 64Kbit/s is used"
AD0/3 AD0/2 CRS
TRI
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ST5451
4 - WORKING PROCEDURES 4 - 1 - RECEIVE FRAME Recognized frame (by means of SAPI and/or TEI identification), having a minimum length is stored in the RFIFO with all bytes between the opening flag and CRC field. When the frame is less than or equal to 32 bytes, is transferred in one block, and just after the receiving completion interrupt (RME), a status byte is appended at the end. The frame and its status byte remain stored until P acknowledgement (RMC). When the frame is longer than 32 bytes, blocks of 32 bytes plus one remainder block of lenght 1 to 32 are transferred to the microprocessor. The receiving 32 byte block generates a RPF interrupt and the data in RFIFO remains valid until P acknowledgement (RMC). The P can ignore a received frame by meaning RMD (Receive Memory Delete), reaction to RPF or RME. The part of frame already stored is deFigure 1: Receiving of an HDCL frame leted and the remainder frame is ignored by the HDLC Controller. The last block of the frame generates the RME interrupt. RFBC register bits 0 to 4 indicate the number of bytes currently stored in the RFIFO. Bits 5 to 7 indicate the total number of 32 byte blocks already received. Bits 5 to 7 do not overflow. When the counter status 7 has been reached, it indicates a frame length greater than 223 bytes (see Table 3). RFBC register is valid only after the RME interrupt and remains valid until RMC acknowledgement by P. At each read access by the P, RFBC 5/7 bits remain unchanged, RFBC 0/4 bits are decreased to reach value 0 when the whole block is read. Interrupts are queued inside the device. They are sent one by one to the microprocessor after each acknowledgement RMC. If a frame is lost because the RFIFO was full, a RFO interrupt is generated.
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ST5451
4- 2 - TRANSMIT FRAME After polling bit XFW or after a XPR interrupt, up to 32 bytes may be stored in XFIFO. Transmission begins after that XHF command is issued by P. ST5451 will request another data block by an XPR interrupt if the XFIFO contains less than 32 bytes. When XME is set, all remaining XFIFO bytes are Figure 2: Transmission of an HDCL frame transmitted, the CRC field and the closing flag are added. The HDLC controller then generates a new XPR interrupt. If the XFIFO becomes empty while XME command has not been set, an abort sequence is generated, followed by interframe time fill and XDU interrupt is generated. A frame may be aborted by XRES command as well.
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ST5451
4 - 3 - COMMAND/INDICATE PROCEDURE The exchange of information in the C/I channel runs as follows: The two circuits (i.e. ST5421 and ST5451) connected on the GCI interface send one each other a permanent four bit command code in C/I field. RECEIVE C/I The ST5451 stores on every frame the four bits of C/I channel coming from level 1 circuit in a first register CIR. This value is compared with the previous one. If a one new appears during two consecutive frames, this new value is loaded in register CIR1 and a CIC1 interrupt is generated. TRANSMIT C/I The transmit register CIX1 can be written at any time by the P. Its content is continuously sent in the C/I channel. Note: The TIM command (0000) forces a low level on DOUT, if CIR1 = DI (1111) when VZ DOUT = 1 to require FS and CLK. 4 - 4 - MONITOR CHANNEL The GCI Monitor channel procedure allows full duplex data transmission with acknowledgement using A bit. MESSAGE RECEIVING An interrupt (bit RMR1 in ISTA1 register) is generated when a new byte is available in register MONR1. ST5451 generates an interrupt bit (XAB1 in ISTA1) if it does not read twice the same bytes meanwhile sending an ABORT to the remote transmitter. It performs an interrupt (EOM in ISTA1) also when it has received an End Of Message. Acknowledgement to remote transmitter is sent if: - the byte was received twice with the same value - the microprocessor reads the previous byte stored in register MONR1. This procedure performs flow control between S interface device and P. MESSAGE TRANSMISSION ST5451generates an interrupt (XMR1 in ISTA1) when register MONX1 is available. Writing register MONX1/0 generates a message transmission. When the last byte is stored in the register MONX1/1, ST5451 sends the End of Message to remote receiver. If an Abort is received, one interrupt (RAB1) is generated. 4 - 5 - M' and C/I' CHANNELS The procedure allows a full duplex data transmission between microprocessor and the peripheral devices connected on C/I' local and M' channel through GCI-SCIT channel 1. Receive Interrupt on C/I' (DOUT is an input). A new value on C/I' indicates to ST5451 master
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that one device in the terminal wants to send a message. Up to six peripherals may generate such an interrupt to the microprocessor. ST5451 writes at every frame the six bits of C/I' channel coming from peripherals in register CIR'. This value is compared with the previous one and if a new one appears during two consecutive frames, is loaded in register CIR2 and CIC2 interrupt (ISTA2 register) is generated. P may send a message on M' channel (DIN becomes an output) to allow the peripheral device to transmit. MESSAGE TRANSMISSION ON M' CHANNEL ST5451 sets interrupt XMR2 (ISTA2 register) if register MONX2/0 is available. Writing MONX2/0 generates a message transmission. When the last byte is stored in register MONX2/1, ST5451sends End of Message to remote peripheral. If an ABORT is received, interrupt RAB2 (ISTA2 register) is issued. Then microprocessor may send its message again. MESSAGE RECEPTION ON M' CHANNEL Interrupt bit RMR2 (ISTA2 register) is generated when a new byte is available in MONR2 register. ST5451 sets interrupt bit XAB2 (ISTA2 register) if it does not read twice the same byte; in this case, it sends an ABORT to remote peripheral. The controller generates interrupt bit EOM2 (ISTA2 register) when End Of Message is received. 4 - 6 - ACCESS PROCEDURE TO D AND C/I CHANNELS (GCI and TE mode selected only) Up to eight HDLC controllers may be connected to D channel and C/I channel. A contention resolution mechanism is used if bit CMS (Contention Mode Selection) is set. The mechanism allows to give an access without losing data. An access request may be generated, if CIX1 (Command/Indicate Register 1) contains a different code from DI (1111). During the procedure, M channel (with A and E bits) may be used. On input DIN, the GCI controller checks the CMS4 bit (CMS channel - Third GCI channel) (see Fig. 4). CMS4 indicates the status of C/I and D channels CMS4= 1 "channels free"; CMS4= 0 channels occupied. If the channels are free, the HDLC controller starts transmitting its individual address AD2 on CMS1, AD1 on CMS2, AD0 on CMS3. If an erroneous address is detected, the procedure is terminated immediately. If the complete address can be read without error, the D and C/I channels are occupied: the ST5451 transmits CMS4 = 0: The HDLC controller which has the lowest address has priority over the others. The access request is withdrawn if the HDLC controller transmits code DI = 1111. the CMS4 bit (CMS field) is set.
ST5451
Figure 3: GCI-SCIT Frame Timing
Figure 4: GCI-SCIT Channels Timing
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ST5451
4 - 7 - DMA ACCESS The HDLC controller has a DMA interface which is activated by DMA bit in MODE register.The DMA interface is available only when multiplexed bus is selected. ST 5451 asserts DMA REQR or DMA REQX to request an exchange of bytes between the FIFOS and the external memory. The external DMA controller asserts DMA ACKR or DMA ACKX to access the FIFOS. These signals are equivalent to E/DS/RD functions. During DMA access, CS/CE pin must be inactive; AS and E/DS/RD signals can be present. Outside DMA Access, all registers are accessible Figure 5: D and C/I channels Access Procedure by the P except the FIFOS. FRAME RECEPTION: When one block has been stored in RFIFO, DMA REQ R pin goes low and RPF (or RME) interrupts the P. The DMA controller reads the RFIFO. After the RME interrupt, the frame length will be available in RFBC register. The block is acknowledged by RMC command. FRAME TRANSMISSION: When a 32 byte block is free in XFIFO, DMA request goes low and XPR interrupts the P. The DMA controller can write data in the XFIFO. At the end of the frame, the P send XME to HDLC controller; CRC and closing flag will be sent by the HDLC controller.
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4 - 8 - INTERRUPT PROCEDURE 4 - 8 - 1 - HDLC CHANNELS 4 - 8 - 1 - 1 - RECEIVE DIRECTION RRE and RPF interrupts RPF bit (register ISTA0) set high to indicate the HDLC controller has received a block of 32 bytes which is not a complete message. This bit remains high until it is erased by the microprocessor. As for each bit of ISTA0 register, except the extension bits of ISTA1 and ISTA2 (EXI1, EXI2), the way to erase RPF is to write a "0" at its location and to write a "1" at the location of the others (for example 7FH into ISTA0 to erase RME). The processing order is: - put Mask0 on ISTA0 (if Mask Off) - (Read FIFOR) X 32 - Write ISTA0 to erase RPF (BFH) - Write RMC to "1" for asking for another block of the frame (NB: RMC, RMD are automatically erased by the controller) - Remove Mask0 RME bit (register ISTA0) set high to indicate the HDLC controller has received a short frame or the last block of a large frame. The message is now complete, the bit remains high until it is erased by the microprocessor. The processing order is: - put Mask0 on ISTA0 (if upper level Mask Off) - Read RFBC with a mask on the 3 most significant bits, to know the number "N" of transfers to do - (Read FIFOR) x N for data - Read FIFOR for status on the frame - Write ISTA0 to erase RME (7FH) - Write RMC or RMD to "1" for asking for another frame. RF0 interrupts RF0 is a bit of the interrupt register ISTA0 set high to indicate an overflow of the receive FIFO has been detected, either because more than 8 frames cannot be stored or because more than 64 bytes can't be stored. This information is also stored into the status of the concerned frame (RDO). The processing order of the microprocessor is: - Looking for RPF and RME bits and pop - up the frames. Then look for the status and throw down the frame concerned. In general case, only one frame is lost. 4 - 8 - 1 - 2 - TRANSMIT DIRECTION XPR Interrupt XPR is a bit of the interrupt register ISTA0 coming high to indicate HDLC controller has a free block of 32 bytes. This bit remains high until the microprocessor write a byte into the block and erase this bit into ISTA0; if another block is free, XPR get high again immediately. The processing order of the microprocessor is in non DMA Mode: - Put Mask0 on ISTA0 (if upper level Mask Off) - Write at least one byte into FIFOX - Write ISTA0 to erase XPR - Write XHF to "1" for launching the transmit operation of block (a block is not necessarily 32 bytes) or write XME to "1" for launching the transmit of a short frame or of the last part of a frame - Remove masks In DMA Mode two general cases are possible: 1) The external DMA controller works by "pages" less or equal to 32 bytes. The "process" of the DMAC is a short frame transmission and the processor must give an XME at the end of the DMAC process (refer to figure 2). 2) The DMA controller works by "pages" of more than 32 bytes. It's process is the transfer of the whole frame. The circuit doesn't need an XHF at the end of an intermediate 32 byte block; since it has reached 32 bytes written into the current fifo, it begins the transfer and toggles on the second fifo as soon as the first is full. (At this moment an XME is possible if the 32nd byte was the end of the frame case 1) and then, a 33rd write operation into the fifo generates an internal XHF and the frame following blocks are expected. - In the two cases the flow control is done between DMAC and ST5451 by the way of REQX and ACKX signals The processing order is: - Put Mask0 - Give order to DMAC to begin transfer - Wait for DMAC end of process - Write ISTA to erase on XPR - Write XME to signal the end of the frame to the ST5451 (otherwise the ST5451 will put "underrun" interrupt, as soon as its two blocks are free). XDU Interrupt XDU is a bit of the interrupt register ISTA0 coming high to indicate HDLC controller has detected an underrun (a frame is being transmitted and no more bytes are available into the FIFO). The HDLC controller finish the frame by transmitting an "Abort" and no more data can be transmitted even in NHF mode. To be sure XDU is seen by the MIcroprocessor, XDU interrupt bit must be erased in ISTA0 in addition of XRES security procedure The transmit control is frozen and the only way to reinitialize a transmit session is to write an XRES, after erasing XDU.
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4 - 8 - 2 - M CHANNELS INTERRUPTS EOM, RMR, XMR, RAB Receive Direction RMR 1/2 is a bit of interrupt register ISTA 1/2 coming high to indicate the M (or M') channel controller has received a valid byte on receiving channel (two identical consecutive bytes). The microprocessor processing order is; 1. Erasing RMR 1/2 interrupt into ISTA 1/2 2. Read MONR 1/2 register. This order can't be inverted because, as long as MONR isn't read, the receive state machine is locked in wait state, a new byte can't be acknowledged and so, a new interrupt can't be done. More, if MONR is read first, the receive state machine is ready for receiving a new byte and create another interrupt. So, if the interrupt bit corresponding to the previous frame isn't erased before a new byte arrives, this byte won't be seen (the microprocessor won't be informed) and the controller will be locked waiting for MONR read. XAB 1/2 is a bit of the interrupt register coming high to indicate the receive controller has detected an abort (two conscutive bytes not identical) as long as this interrupt isn't erased, the receiver is locked in wait state. EOM 1/2 is a bit of the interrupt register coming high to indicate the receive controller has detected an end of message. As long as the interrupt isn't erased, the receiver is locked in wait state. Transmit Direction XMR 1/2 is a bit of the interrupt register coming high to indicate a byte can be written into MONX. The processing order is: 1. Erasing XMR bit 2. Writing a new byte into MONX. If this order is inverted, the new byte will be transmitted and a new XMR may be erased before being seen by the microprocessor. RAB 1/2 is a bit of the interrupt register coming high to indicate the remote receiver has reported an abort detection. The processing order is: 1. Erasing RAB bit 2. Erasing XMR bit 3. Writing a new byte into MONX. If a write operation of the new byte is done before the RAB erasing, the byte will be lost and the transmitter will stay waiting for it. 4 - 8 - 3 - CI CHANNEL INTERRUPTS CIC 1/2 is a bit of ISTA 1/2 interrupt register coming high to indicate a valid byte has been detected by the command indicate receive controller, and readable into CIR 1/2 register. The processing order is: 1. Erasing CIC bit 2. Reading CIR register. If this order is inverted, a next byte may be unseen by the microprocessor. It is recommended to work with "Ping Pong" protocol on CI channels, as non flow control is done. 4 - 9 - SOFTWARE RESET PROCEDURES 4 - 9 - 1 - XRES (Transmit Direction) XRES is a level sensitive command of CMDR which initialize the transmit process. - XPR interrupt bit is erased - XDU interrupt bit is not erased (security procedure) - All data in FIFOs are lost - After an XRES, the microprocessor must wait for an XPR before writing new data. The processing order is: - Writing a "1" into XRES (CMDR) - Writing a "0" into XRES (CMDR) - Read ISTA0 waiting XPR or enable XPR interrupt 4 - 9 - 2 - RHR (Receive Direction) RHR is a level sensitive command of CMDR, which reinitialize the receive process. - RME, RPF bits are erased - RFO bit is erased - All frames in FIFO R are lost - If RHR is released (got down) at the time a frame is on line, the HDLC controller waits for a flag. 4 - 9 - 3 - M1RES, M2RES M/CI channels MRES is a level sensitive command of CMDR which initialize the M/CI channel protocole in both directions. XMR, RAB, RMR, CIC, XAB, EOM bits are erased by MRES. After a clock programming (bit CRS), it's necessary to put MRES bit to initialize properly the M protocol.
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TYPICAL APPLICATIONS ST5451 HDLC controller may be used in TE, NT2, NT12 or LT. Figures 6 to 8 illustrate three typical applications in multifunctional TE. The D channel containing only signalling is processed by the LAPD controller and routed via a parallel P interface to the terminal processor. The support of the LAPD protocol which is implemented by the HDLC controller device allows in cost senstive applications the use of a low cost microprocessor. See fig. 6. Fig. 7 illustrates a configuration in which the D channel containing signalling data (SAPI s) as well as packet switched data (SAPI p) is processed by two controllers and two independent microprocessors. Fig. 8 illustrates a configuration in which one microprocessor is connected to two controllers via a DMA controller. D channel with LAPD signalling data and B chanFigure 6: Low cost GCI terminal application nel LAPB packet data are processed by the same P. A DMA controller performs device to memory transfers. It is a typical work station application. Fig. 9 and 10 illustrate 2 typical applications in NT2 or exchange. An NT2 or LT in fig.9 with eight D channel controllers connected to the GCI interface handle subscriber 0 to 7. Any GCI compatible transceiver (S or U) may be used to do the subscriber line interface; a GCI compatible exchange circuit may implement the system interface. This is one decentralized application. Fig. 10 illustrates a centralized application. Using a switching net work, it is possible to connect: up to thirty two 64 Kbit/s channels on a 2 Mb/s PCM highway to 32 B channel controllers up to sixty four 64 Kbit/s channels on a 4 Mb/s PCM highway to 64 B channel controllers up to two hundred fifty six D channels on a 4 Mb/s highway to 256 D channel controllers.
S - INT
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Figure 7: LAPB and LAPD protocol on the same D channel handlended with 2 different Ps
S - INT
Figure 8: LAPB and LAPD protocol handling an B and D channel
S - INT
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FIgure 9: Decentralized D channel handling in NT2 or LT
Figure 10: Centralized D channel handling in NT2 or LT
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Figure 11: HDCL Frame Transmission Procedure
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Figure 12: HDCL Frame Transmission Procedure in D Channel
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Figure 13: S Activation and Deactivation procedure
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ELECTRICAL CHARACTERISTICS (T from 0 to 70C, VDD = 5 0.25V).
Symbol IS Parameter Supply Current Test Condition CLK Freq. = 4MHz CLK Freq. = 2MHz NO CLK Freq. Min. - - - Typ. 4 2 20 Max. - 4 300 Unit mA mA A
STATIC CHARACTERISTICS - GCI INTERFACE (T from 0 to 70C, VDD = 5 0.25V).
Symbol VIH VIL VOH VOL VOL C COUT Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Low Level Output Voltage DOUT . Din . INT Input/Output Capacity Load Capacity DIN/DOUT Load Capacity INT Load Capacity AD0/7 Condition Maximum leakage current : 10 A IOH = -0,4 A IOL = 2mA IOL = 7mA Maximum leakage current : 10 A Min. 2.4 VSS-0,4 2,4 0,45 0,45 10 150 150 100 Max. VDD+0,4 0,8 Unit V V V V V pF pF pF pF
DYNAMIC ELECTRICAL CHARACTERISTICS - GCI Interface
Symbol FSync FCLK tWCH tWCL tRC tFC tHCF tSFC tDCD tDCZ tDFD tSDC tHDC 8 KHz 64 x n x FSync 1 n 8 Period of CLK High Period of CLK Low Rise Time of CLK Full Time of CLK Hold Time: CLK - FS Set-up Time: FS - CLK Delay Time: CLK High to data valid. out: 150 pF Delay Time: to Data Disabled Delay Time: FSync. High to data valid. count: 150 pF. Applies only if Sync rises later than CLK raising edge. Set-up Time: Data valid to CLK receive edge. Hold Time: CLK low to data invalid. 30 30 0 0 30 80 80 80 512 80 80 10 10 Parameter Min. Typ. 8 4096 Max. Unit KHz KHz ns ns ns ns ns ns ns ns ns ns ns
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DYNAMIC ELECTRICAL CHARACTERISTICS - Double Clock Interface
Symbol FSync FCLK tWCH tWCL tRC tFC tHCF tSFC tDCD tDCZ tDFD tSDC tHDC 8 KHz 16 x n x FSync 1 n 64 Period of CLK High Period of CLK Low Rise Time of CLK Full Time of CLK Hold Time: CLK - FS Set-up Time: FS - CLK Delay Time: CLK High to data valid. out: 150 pF Delay Time: to Data Disabled Delay Time: FSync. High to data valid. count: 150 pF. Applies only if Sync rises later than CLK raising edge. Set-up Time: Data valid to CLK receive edge. Hold Time: CLK low to data invalid. 30 30 0 0 30 80 80 80 128 50 50 10 10 Parameter Min. Typ. 8 8192 Max. Unit KHz KHz ns ns ns ns ns ns ns ns ns ns ns
ELECTRICAL CHARACTERISTICS - Single Clock Interface
Symbol FSync FCLK tWCH tWCL tRC tFC tHCF tSFC tDCD tDCZ tDFD tSDC tHDC 8 KHz 8 x n x FSync 1 n 64 Period of CLK High Period of CLK Low Rise Time of CLK Full Time of CLK Hold Time: CLK - FS Set-up Time: FS - CLK Delay Time: CLK High to data valid. out: 150 pF Delay Time: to Data Disabled Delay Time: FSync. High to data valid. count: 150 pF. Applies only if Sync rises later than CLK raising edge. Set-up Time: Data valid to CLK receive edge. Hold Time: CLK low to data invalid. 30 30 0 0 100 80 80 80 64 80 80 10 10 Parameter Min. Typ. 8 4096 Max. Unit KHz KHz ns ns ns ns ns ns ns ns ns ns ns
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Figure 14: GCI Timing
Figure 15: Single Clock Diagram
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Figure 16: Non-multiplexed P bus timing
READ CYCLE (Non-multiplexed mode)
Symbol tEAH tEAH tAES tAES tACC tDF tWE Address Hold After E R/W Hold After E Address to E Setup R/W to E. Setup Data Delay from E Output Float Delay Minimum Width of E 110 Parameter Min. 10 10 20 20 110 25 Max. Unit ns ns ns ns ns ns ns
WRITE CYCLE (Non-multiplexed mode)
Symbol tEAH tEAH tAES tAES tDES tEDH tWE tRW Address Hold After R/W Hold After E Address to E Setup R/W to E.CS Setup Data to End of E Setup End of E.CS to Data hold Minimum Width of E Minimum Width of RESET Parameter Min. 10 10 20 20 35 10 60 100 Max. Unit ns ns ns ns ns ns ns ns
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Figure 17: Multiplexed Intel-like P bus timing
READ CYCLE (Multiplexed Intel Mode)
Symbol tLA tAL tRD tRR tDF tRI tWA tCSS tCSH Address Hold After ALE Address to ALE Setup Data Delay from RD RD Pulse Width Output Float Delay RD Control Interval ALE Pulse Width CE to RD or WR set-up tCSS CE hold after RD to WR tCSH 70 30 20 10 110 25 Parameter Min. 10 20 110 Max. Unit ns ns ns ns ns ns ns ns ns
WRITE CYCLE (Multiplexed Intel Mode)
Symbol tww tDW tWD tWI WR Pulse Width Data Setup to WR Data Hold after WR WR Control Interval Parameter Min. 60 35 10 70 Max. Unit ns ns ns ns
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Figure 18: Multiplexed Motorola-like P bus timing
Symbol tWAS tWDS tASDS tRWS tRWH tCSS tCSH tAAS tAAH AS Pulse Width DS Pulse Width AS low to DS high RW to DS setup RW hold after DS CS to DS setup CS hold after DS Address to AS setup Address hold after AS
Parameter
Min. 30 110 10 20 10 20 10 20 10
Max.
Unit ns ns ns ns ns ns ns ns ns
READ CYCLE
Symbol tDV tDF Data Valid after DS Output Flat Delay Parameter Min. Max. 110 25 Unit ns ns
WRITE CYCLE
Symbol tDWS tDWH Data to DS setup Data Hold after DS Parameter Min. 35 10 Max. Unit ns ns
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DMA BUS TIMING (Reception Mode)
Symbol tACC tDF tWAR tWAR tDRAR Data Delay from ACKR Output Float Delay Minimum width ACKR Minimum width ACKR REQR Delay from ACKR 110 70 80 Parameter Min. Max. 110 25 Unit ns ns ns ns ns
Figure 19: DMA frame reception timing
Figure 20: DMA frame transmission timing
DMA BUS TIMING (Transmission Mode)
Symbol tDAS tDAH tWAX tWAX tDRAX Data Setup to ACKX Data Hold from ACKX Minimum width ACKX Minimum width ACKX REQX Delay from ACKX Parameter Min. 35 10 60 70 80 Max. Unit ns ns ns ns ns
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DEN TIMING
Symbol tDRCS tDRCH tDFCS tDRCH DEN setup to CLK DEN Hold from CLK DEN Setup to CLK DEN Hold from CLK Parameter Min. Max. 30 30 30 30 Unit ns ns ns ns
Figure 21: DEN Timing
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mm MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 1.27 16.51 7.6 1.27 0.291 0.016 0.1 0.35 0.23 0.5 45 (typ.) 18.1 10.65 0.697 0.394 0.050 0.65 0.299 0.050 0.713 0.419 TYP. MAX. 2.65 0.3 0.49 0.32 0.004 0.014 0.009 0.020 MIN. inch TYP. MAX. 0.104 0.012 0.019 0.013
DIM.
OUTLINE AND MECHANICAL DATA
SO28
8 (max.)
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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